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串口的verilog程序

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:02:38 06/13/2012 
// Design Name: 
// Module Name:    uart_tx 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module uart_tx(
    input clk,
input rst,
input [7:0] dat,
input stb,
    output reg tx
    );

parameter state0 = 4'd0;
parameter state1 = 4'd1;
parameter state2 = 4'd2;
parameter state3 = 4'd3;
parameter state4 = 4'd4;
parameter state5 = 4'd5;
parameter state6 = 4'd6;
parameter state7 = 4'd7;
parameter state8 = 4'd8;
parameter state9 = 4'd9;

parameter state10 = 4'd10;
parameter state11 = 4'd11;
parameter state12 = 4'd12;
parameter state13 = 4'd13;
parameter state14 = 4'd14;
parameter state15 = 4'd15;

//reg complete;
reg [7:0] shifter;
reg [12:0] counter;
reg state_change;
reg [3:0] state;

reg reg_stb;
reg reg_stb0;
reg reg_stb1;
reg reg_stb2;
reg reg_stb3;
//reg sck;

always @(posedge clk)
begin
    counter <= counter - 1'B1;
if(rst)
begin
    reg_stb0 <= 0;
 reg_stb1 <= 0;
 reg_stb2 <= 0;
 reg_stb3 <= 0;
//  sck <= 0;
        state <= state0;
 counter <= 1'B0;
 state_change <= 1'B0;
 shifter <= 8'B1111_1111;

end
else if(counter == 0) state_change <= 1'B1;
    else if(state_change == 1'B1)  
    begin
case(state)  
    state0:begin
reg_stb0 <= stb;
reg_stb1 <= reg_stb0;
reg_stb2 <= reg_stb1;
reg_stb3 <= reg_stb2;             
            reg_stb <= reg_stb0 && reg_stb1 && ~reg_stb2 && ~reg_stb3; //检测下降沿沿(仔细思考)
if(reg_stb == 1)
begin
    shifter <= dat[7:0];
    state <= state1;
 state_change <= 0;
 counter <= 1;
//  sck 
end
else
begin
    state <= state0;
 state_change <= 0;
 counter <= 1;  
               end
           end

 state1:begin
// sck <= 0;
tx <= 1'B1;         //起始位 0
counter <= 5208;    //50MHZ的晶振,每个时钟周期为20ns;波特率9600的每个数据位时间为1/9600,故需要5208个时钟周期
state <= state +1'B1;
state_change <= 1'B0;
end 

 state2:begin
//             sck <= 1;
tx <= 1'B0;         //起始位 0
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state3:begin
//             sck <= 0;
tx <= shifter[0];         //数据位dat[0]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state4:begin
//             sck <= 1;
tx <= shifter[1];        //数据位dat[1]
counter <= 5208;
state <= state +1;
state_change <= 0;
 
end

 state5:begin
//             sck <= 0;
tx <= shifter[2];        //数据位dat[2]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state6:begin
//             sck <= 1;
tx <= shifter[3];       //数据位dat[3]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state7:begin
//             sck <= 0;
tx <= shifter[4];        //数据位dat[4]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state8:begin
//             sck <= 1;
tx <= shifter[5];         //数据位dat[5]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state9:begin
//             sck <= 0;
tx <= shifter[6];        //数据位dat[6]
counter <= 5208;
state <= state +1'B1;
state_change <= 1'B0;
 
end

 state10:begin
//             sck <= 1;
tx <= shifter[7];           //数据位dat[7]
counter <= 5208;
state <= state + 1'B1;
state_change <= 1'B0;  

end

 state11:begin
//             sck <= 0;
tx <= 1'B1;         // 停止位         
counter <= 5208;
state <= state0;
state_change <= 1'B0;  

end

 default:begin
//             sck <= 1;
counter <= 1'B1;
state <= state0;
state_change <= 1'B0;
                       
end
           endcase

       end

end
endmodule









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